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VHDL Decoder 3to8


Difficulty:
1/5


This is a quite old (circa 2014) university project of mine.

This project entails assembling a hardware decoder circuit with 3 input & 8 outputs in VHDL and simulating it using Altera's Quartus II software.

quartus vhdl simulation

I used Windows 8.1 x86_64 and Quartus II 8.1 Web Edition - Student Edition. You need to have Quartus II 8.1 Web Edition or higher to run it.

Github

Github repository link.


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