Author image

VHDL Decoder 3to8


Difficulty:
1/5


This is a pretty old vhdl university project made with. Creating a decode 3 input 8 outputs in vhdl and simulating it in Altera Quartus II software.

I used Windows 8.1 x86_64 and Quartus II 8.1 Web Edition - Student Edition. You need to have Quartus II 8.1 Web Edition or higher to run it.

quartus vhdl simulation

Github

Github repository link.


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